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TU BCA First Semester: Digital Logic (CACS105) — Complete Syllabus Overview
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TU BCA First Semester: Digital Logic (CACS105) — Complete Syllabus Overview

Digital Logic is one of the five core courses in the First Semester of the Bachelor of Computer Applications (BCA) programme under Tribhuvan University’s Faculty of Humanities and Social Sciences (TU FOHSS). The course carries the code CACS105, is worth 3 credit hours, and runs with a class load of 5 hours per week — 3 hours theory and 2 hours practical (lab). It is offered alongside Computer Fundamentals and Applications (CACS101), Society and Technology (CASO102), Mathematics I (CAMT104), and English I (CAEN101) in the First Semester.

The course introduces students to the fundamental principles of digital electronics and logic circuit design — the hardware foundation upon which all digital computers are built. Topics range from digital signals and number systems through Boolean algebra, combinational logic circuit design, programmable logic devices, sequential circuits (flip-flops, counters, registers) to formal sequential logic design methodology. Both the theory and lab components run simultaneously, so students verify every circuit concept on actual hardware (integrated circuits on project boards) within days of covering it in theory.

Subject Information at a Glance

  • Course Title: Digital Logic
  • Course Code: CACS105
  • Credit Hours: 3 credits
  • Year/Semester: I/I (First Year, First Semester)
  • Class Load: 5 hours per week — Theory: 3 hours + Practical: 2 hours
  • Full Marks: 60 (Theory) + 20 (Practical) + 20 (Internal Assessment) = 100 total
  • Pass Marks: 24 (Theory) — Theory, Practical, and Internal must all be passed separately
  • Theory Exam Format: Group A — 10 MCQs × 1 mark (10); Group B — attempt any 6 from 7 short questions × 5 marks (30); Group C — attempt any 2 from 3 long questions × 10 marks (20)
  • Practical Assessment: Practical viva (10) + Lab reports (5) + Lab attendance (5) = 20 marks
  • Examination: Semester-based (end-of-semester exam conducted by TU FOHSS, Dean’s Office)
  • Conducting Institution: Faculty of Humanities and Social Sciences (FOHSS), Tribhuvan University

Why Digital Logic?

Digital Logic is the hardware foundation of every digital device you use — from the smartphone in your pocket to the servers powering Nepal’s banking, telecommunications, and government systems. Every computer — regardless of how sophisticated its software — ultimately executes binary operations on transistor-based logic circuits. Understanding digital logic means understanding how computers actually work at the level of 1s and 0s: how binary arithmetic is performed in hardware, how decisions are made using logic gates, how memory elements store state using flip-flops, and how sequences of operations are coordinated using counters and registers.

For TU BCA students, Digital Logic serves as the essential bridge between the software-focused curriculum (C programming, data structures, databases) and the hardware reality that software runs on. The concepts learned in CACS105 directly underpin the Microprocessor and Computer Architecture course (CACS157) in Second Semester, and provide the theoretical foundation for understanding operating systems, computer organization, and embedded systems in later semesters. Students who master Digital Logic find that their intuition for why computers behave the way they do — in terms of memory, processing, binary representation, and timing — becomes significantly sharper.

CACS105 Theory Syllabus — Unit-wise Detail

Unit 1: Introduction (2 teaching hours)

  • Digital Signals and Waveforms: analog vs. digital signals — analog (continuous variation — sound waves, temperature, pressure); digital (discrete states — binary: HIGH and LOW); advantages of digital over analog (noise immunity, ease of storage, processing, and transmission, precision, reproducibility); digital signal representation using voltage levels (TTL logic — HIGH: 2.4–5V, LOW: 0–0.8V; CMOS logic — varying thresholds depending on supply voltage)
  • Pulse waveform parameters: rise time (time for signal to rise from 10% to 90% of HIGH level), fall time (time for signal to fall from 90% to 10%), pulse width (time between 50% points of rise and fall), period (T — time between corresponding points of successive pulses), frequency (f = 1/T — in Hz), duty cycle (ratio of pulse width to period — expressed as percentage: DC% = (t_W/T) × 100); ideal vs. non-ideal pulses
  • Digital Logic and Operations: binary logic values (1 and 0, TRUE and FALSE, HIGH and LOW); basic logic functions — NOT (complement/inverter — output is opposite of input), OR (output HIGH if any input HIGH), AND (output HIGH only if all inputs HIGH); truth tables as the complete specification of a logic function
  • Digital Computer and Integrated Circuits (IC): digital computer as a system of interconnected logic circuits; role of integrated circuits (ICs) in modern digital design; IC complexity levels — SSI (Small Scale Integration — less than 12 gates per chip, e.g., 7400 NAND gate quad), MSI (Medium Scale Integration — 12–99 gates, e.g., 7483 4-bit adder, 74138 decoder), LSI (Large Scale Integration — 100–9,999 gates, e.g., calculator chips, memory chips), VLSI (Very Large Scale Integration — 10,000+ gates, e.g., microprocessors, FPGAs); IC packaging — DIP (Dual Inline Package — most common in BCA labs), SOP, QFP, BGA; IC nomenclature — reading datasheet information (part number, logic family, pin diagram, truth table, electrical characteristics, Vcc and GND pins)
  • Clock Waveform: the clock as the heartbeat of synchronous digital systems; free-running oscillator generating square wave; clock period and frequency; clock distribution in digital systems; synchronous vs. asynchronous operation; why a clock is needed (coordinates all state changes to occur simultaneously at clock edges — prevents race conditions); rising edge vs. falling edge triggering

Unit 2: Number System (5 teaching hours)

  • Introduction to Number Systems: positional (weighted) vs. non-positional number systems; positional notation — value = Σ(digit × base^position); four number systems used in digital computing:
    • Decimal (base 10): digits 0–9; human-natural system
    • Binary (base 2): digits 0 and 1; natural language of digital computers (two voltage levels); positional notation example: (1101)₂ = 1×2³ + 1×2² + 0×2¹ + 1×2⁰ = 8+4+0+1 = 13
    • Octal (base 8): digits 0–7; convenient shorthand for binary (3 bits per octal digit)
    • Hexadecimal (base 16): digits 0–9 and A–F (A=10, B=11, C=12, D=13, E=14, F=15); most compact shorthand for binary (4 bits per hex digit); widely used in programming (memory addresses, colour codes — #2C3E50)
  • Number System Conversions (integer and fractional parts):
    • Decimal to Binary: repeated division by 2 (integer part — remainders read upward), repeated multiplication by 2 (fractional part — integer parts read downward)
    • Binary to Decimal: weighted positional notation (multiply each bit by 2^position, sum)
    • Decimal to Octal: repeated division by 8; decimal to hexadecimal: repeated division by 16
    • Octal to Decimal, Hexadecimal to Decimal: weighted positional notation
    • Binary to Octal: group bits in threes from binary point (left for integer, right for fraction); each group converts directly to one octal digit
    • Binary to Hexadecimal: group bits in fours from binary point; each group converts to one hex digit
    • Octal to Binary, Hexadecimal to Binary: expand each digit to 3 or 4 binary digits respectively
    • Octal ↔ Hexadecimal: convert through binary as intermediate
    • Floating point conversions: applying the above methods to both integer and fractional parts separately
  • Representation of Signed Binary Numbers:
    • Sign-magnitude representation: leftmost (MSB) bit is sign bit (0=positive, 1=negative); remaining bits are magnitude; range for n bits: −(2^(n−1)−1) to +(2^(n−1)−1); problem — two representations of zero (+0 and −0); arithmetic is complex
    • 1’s complement: positive numbers same as sign-magnitude; negative numbers obtained by inverting all bits (complementing) of the positive number; still two zeros; range: −(2^(n−1)−1) to +(2^(n−1)−1)
    • 2’s complement (most widely used): positive numbers same; negative numbers obtained by inverting all bits then adding 1 (or equivalently: copy bits right-to-left until first 1 inclusive, then invert remaining bits); single zero; range: −2^(n−1) to +(2^(n−1)−1); for 8-bit: −128 to +127; simplifies arithmetic (subtraction = addition of 2’s complement; no sign handling needed); how modern computers represent integers
    • Floating-point format: IEEE 754 concept — sign bit, exponent field (biased/excess notation), mantissa/fraction field; single precision (32-bit: 1 sign + 8 exponent + 23 mantissa), double precision (64-bit: 1 + 11 + 52); normalized form; representing real numbers in hardware
  • Binary Arithmetic:
    • Binary addition: rules (0+0=0, 0+1=1, 1+0=1, 1+1=10 — carry 1); multi-bit addition with carry propagation
    • Binary subtraction: rules; borrow propagation; subtraction using 1’s complement (add then end-around carry — add carry back to LSB); subtraction using 2’s complement (add 2’s complement of subtrahend; discard carry from MSB — result is correct)
    • Binary multiplication: shift-and-add method; truth table for 1-bit multiplication (same as AND)
    • Binary division: repeated subtraction method
    • Arithmetic with signed 2’s complement numbers: overflow detection (when carry into MSB ≠ carry out of MSB)
  • Binary Coded Decimal (BCD): each decimal digit encoded separately in 4 bits (0000–1001 for digits 0–9; 1010–1111 are invalid/don’t-care BCD codes); example: 47 in BCD = 0100 0111; BCD addition — if sum > 9 (or carry generated), add 0110 (6) to correct and generate a carry; BCD subtraction using 10’s complement; BCD vs. pure binary comparison; applications (calculator displays, digital meters, financial systems where exact decimal representation needed)
  • ASCII Code (American Standard Code for Information Interchange): 7-bit code (128 characters — extended 8-bit ASCII has 256 characters); standard for representing text in digital systems; character groups — control characters (0–31: NUL, BS, HT, LF, CR, ESC, DEL), printable characters — space (32), digits (48–57: ‘0’–’9′), uppercase (65–90: ‘A’–’Z’), lowercase (97–122: ‘a’–’z’), punctuation; ASCII arithmetic: ‘A’=65=41₁₆, ‘a’=97=61₁₆ (lowercase = uppercase + 32); used in C string handling (char type stores ASCII value); Unicode as the modern extension (UTF-8, UTF-16 — supporting Devanagari script — नेपाली text representation)
  • Excess-3 Code (XS-3): each decimal digit represented by its BCD equivalent plus 3 (0011); self-complementing property (9’s complement obtained by inverting all bits — useful in BCD subtraction); example: 6 in XS-3 = 0110+0011 = 1001
  • Gray Code (Reflected Binary Code): consecutive values differ by exactly one bit (unit distance code); eliminates multiple simultaneous bit transitions (reduces noise and glitching in mechanical encoders and ADCs); binary-to-Gray conversion: MSB unchanged; each subsequent Gray bit = XOR of corresponding binary bit and previous binary bit; Gray-to-binary conversion: MSB unchanged; each binary bit = XOR of corresponding Gray bit and previous binary bit; applications — rotary encoders (measuring angular position — e.g., robot joints, steering sensors), optical encoders, ADCs, Karnaugh maps (are arranged in Gray code order — this is why!)
  • Error Detection and Correcting Codes:
    • Parity bit: extra bit appended to make total 1s even (even parity) or odd (odd parity); detects single-bit errors (cannot correct or detect even number of errors); parity bit calculation and verification; applications — memory chips, serial communication
    • Hamming code: error-correcting code that can detect and correct single-bit errors; positions of parity bits (powers of 2 — positions 1, 2, 4, 8…); each parity bit covers specific data bit positions; encoding: computing parity bits; decoding: computing syndrome to identify error position and correct it; Hamming distance concept; (7, 4) Hamming code example (7 total bits — 4 data + 3 parity)
    • Other codes (concept): CRC (Cyclic Redundancy Check — powerful error detection for data blocks, used in Ethernet, ZIP files, storage); checksum; Reed-Solomon code (used in CDs, DVDs, QR codes, deep space communication)

Unit 3: Combinational Logic Design (16 teaching hours — largest unit)

This is the core unit of the course and the most heavily examined. It covers logic gates, Boolean algebra, circuit simplification, and the design and implementation of all major combinational logic building blocks.

3.1 Basic Logic Gates — NOT, OR, AND

  • NOT gate (inverter): one input, one output; output = complement of input; Boolean expression Y = Ā (A-bar); truth table (A=0→Y=1, A=1→Y=0); digital symbol (triangle with bubble); timing diagram; transistor-level implementation (single transistor inverter); NOT as fundamental gate
  • OR gate: two or more inputs; output HIGH if any input HIGH; Y = A + B (+ means OR in Boolean); truth table for 2-input OR; extension to 3-input (Y = A + B + C); digital symbol; timing diagram; positive logic convention
  • AND gate: two or more inputs; output HIGH only if all inputs HIGH; Y = A · B or AB; truth table for 2-input AND; extension to 3-input; digital symbol; timing diagram; Venn diagram interpretation (AND = intersection, OR = union)
  • For each gate: functional expression, circuit diagram (standard IEEE/ANSI symbol), truth table, timing diagram, and Venn diagram representation

3.2 Universal Logic Gates — NAND and NOR

  • NAND gate: NOT-AND; output LOW only when all inputs HIGH; Y = (AB)’ (complement of AND); truth table; digital symbol (AND with bubble); why NAND is universal — any Boolean function can be implemented using only NAND gates; realizing NOT using NAND (connect both inputs together); realizing AND using NAND (NAND + NOT); realizing OR using NAND (De Morgan’s: A+B = (A’·B’)’ = NAND(A’, B’) = NAND-NAND); implementing complete circuits with only NAND gates; NAND implementation of sum of products (SOP) expressions (two-level NAND = AND-OR)
  • NOR gate: NOT-OR; output HIGH only when all inputs LOW; Y = (A+B)’; truth table; digital symbol (OR with bubble); NOR is also universal — realizing NOT, AND, OR using NOR; NOR implementation of product of sums (POS) expressions; two-level NOR = OR-AND; comparison with NAND implementation
  • Why NAND and NOR are preferred in IC implementation — simpler transistor circuit; CMOS NAND/NOR gates are faster and consume less power than AND/OR equivalents (complementary transistor pairs work naturally as NAND/NOR)

3.3 Exclusive-OR and Exclusive-NOR Gates

  • XOR gate (Ex-OR): output HIGH when inputs are different (odd number of 1s); Y = A ⊕ B = A’B + AB’; truth table; digital symbol; timing diagram; properties — A⊕0=A, A⊕1=A’, A⊕A=0, A⊕A’=1, commutative and associative; XOR as “inequality detector”; application — parity bit generation and checking, binary addition (half adder), Gray code conversion, error detection in memory
  • XNOR gate (Ex-NOR): output HIGH when inputs are equal; Y = (A⊕B)’ = AB + A’B’; truth table; digital symbol; application — equality comparator, even parity checker; XNOR as “equality detector”

3.4 Boolean Algebra

  • Introduction: Boolean algebra — mathematical framework for analyzing and designing logic circuits; variables take only two values (0 and 1); developed by George Boole (1854); applied to logic circuits by Claude Shannon (1938 — MIT thesis)
  • Postulates (axioms) of Boolean algebra: definition of 0 and 1; complement; closure; commutativity; associativity
  • Basic Theorems of Boolean algebra (with proof for each):
    • Identity laws: A + 0 = A; A · 1 = A
    • Null laws: A + 1 = 1; A · 0 = 0
    • Idempotent laws: A + A = A; A · A = A
    • Complement laws: A + A’ = 1; A · A’ = 0
    • Double complementation: (A’)’ = A
    • Absorption laws: A + AB = A (proof: A(1+B) = A·1 = A); A(A+B) = A
    • Consensus theorem: AB + A’C + BC = AB + A’C (BC is redundant — consensus term)
    • Involution: as above
  • De Morgan’s Theorems (with proof and application):
    • First theorem: (A+B)’ = A’·B’ (complement of OR = AND of complements); proved by perfect induction (complete truth table); complementing an OR expression: put complement on each variable and change OR to AND
    • Second theorem: (A·B)’ = A’+B’ (complement of AND = OR of complements)
    • Generalization to n variables: (A₁+A₂+…+Aₙ)’ = A₁’·A₂’·…·Aₙ’; (A₁·A₂·…·Aₙ)’ = A₁’+A₂’+…+Aₙ’
    • Application: simplifying complement of complex Boolean expression; converting between NAND and NOR implementations; proving circuit equivalence
  • Principle of Duality: every Boolean theorem has a dual obtained by interchanging AND↔OR and 0↔1 (do not complement variables); duality as a time-saving tool; example — if A+AB=A is a theorem, then A·(A+B)=A is its dual and also a theorem
  • Simplification using Boolean algebra: applying theorems and postulates to reduce the number of literals and gates; worked examples — simplifying expressions like AB + AB’ = A; A + A’B = A + B; (A+B)(A+C) = A + BC
  • Canonical Forms of Boolean expression:
    • Minterm: a product term containing all variables in either complemented or uncomplemented form; for n variables there are 2ⁿ minterms; each minterm corresponds to one row of truth table where output = 1; notation mᵢ where i is decimal equivalent of the variable combination
    • Maxterm: a sum term containing all variables; each maxterm corresponds to one row where output = 0; notation Mᵢ
    • Sum of Products (SOP) canonical form (Sum of Minterms): F = Σm(i, j, k…) — OR of all minterms where F=1; every Boolean function has a unique canonical SOP; example: F(A,B,C) = Σm(1,3,5,7) = A’B’C + A’BC + AB’C + ABC = C (after simplification)
    • Product of Sums (POS) canonical form (Product of Maxterms): F = ΠM(i,j,k…) — AND of all maxterms where F=0; every Boolean function has a unique canonical POS
    • Converting between SOP and POS: missing minterms in SOP = maxterms in POS; F’ minterms = F maxterms
  • Standard SOP and POS (non-canonical): sum of any product terms (not necessarily minterms); product of any sum terms; simplification target

3.5 Simplification of Logic Functions Using Karnaugh Map (K-map)

  • Introduction: K-map (Maurice Karnaugh, 1953) — graphical method for minimizing Boolean expressions; more systematic than algebraic manipulation; limited to 4–6 variables practically; cells arranged in Gray code order so adjacent cells differ by exactly one variable (allows combining)
  • 2-variable K-map: 4 cells arranged in 2×2 grid; labeling; populating with minterms; identifying groups (1-cell, 2-cell = pair)
  • 3-variable K-map: 8 cells in 2×4 grid; rows labeled A, A’; columns labeled BC in Gray code (00, 01, 11, 10); wrap-around adjacency (left/right edges are adjacent); identifying groups of 1s — singles (1 cell — 3 literals), pairs (2 cells — 2 literals), quads (4 cells — 1 literal), octets (8 cells — constant 1); rules: groups must be powers of 2 (1, 2, 4, 8); groups must be rectangular; cells can be in multiple groups; use largest possible groups; minimum number of groups
  • 4-variable K-map: 16 cells in 4×4 grid; rows labeled AB in Gray code (00, 01, 11, 10); columns labeled CD in Gray code; wrap-around both horizontally and vertically (edges and corners adjacent); groups of 1, 2, 4, 8, 16 cells
  • Simplification procedure: (1) plot function on K-map (place 1s for minterms, 0s for maxterms, Xs for don’t-cares); (2) identify all prime implicants (largest possible groups of 1s); (3) identify essential prime implicants (groups covering at least one 1 not covered by any other group); (4) select minimum set of prime implicants covering all 1s
  • SOP simplification: grouping 1s → each group gives one product term in minimized SOP expression
  • POS simplification: grouping 0s → each group gives one sum term in minimized POS expression; complement of grouping 0s and apply De Morgan’s
  • Don’t-care conditions: minterms where output is undefined (either 0 or 1 — don’t care which); marked with X on K-map; can be included in groups to make them larger (reducing literals) but don’t need to be covered; practical sources — BCD (codes 1010–1111 are invalid BCD inputs, treated as don’t-cares)
  • Worked examples: simplifying 3-variable functions in SOP and POS; 4-variable function with don’t-cares

3.6 Implementation of Combinational Logic Functions

  • Half Adder (HA): adds two 1-bit binary numbers; inputs A, B; outputs Sum (S) and Carry (C); truth table; S = A ⊕ B (XOR); C = A·B (AND); logic diagram (1 XOR gate + 1 AND gate); limitation — cannot add carry from previous stage
  • Full Adder (FA): adds three 1-bit binary numbers (A, B, Cin — carry in); outputs Sum (S) and Carry out (Cout); truth table (8 rows); S = A ⊕ B ⊕ Cin; Cout = AB + BCin + ACin = AB + Cin(A⊕B); logic diagram; implementing Full Adder using two Half Adders and one OR gate (key exam question — draw the circuit); 4-bit ripple carry adder — cascading 4 full adders
  • Half Subtractor (HS): subtracts two 1-bit numbers; inputs A (minuend), B (subtrahend); outputs Difference (D) and Borrow (Br); D = A ⊕ B; Br = A’·B; logic diagram
  • Full Subtractor (FS): subtracts three bits (A, B, Bin — borrow in); D = A ⊕ B ⊕ Bin; Bout = A’B + A’Bin + BBin; logic diagram; implementing using two half subtractors

3.7 Encoders, Decoders, Multiplexers, Demultiplexers

  • Decoder: converts binary input code to one-of-many active outputs; n input lines → 2ⁿ output lines; 2-to-4 line decoder (2 inputs → 4 outputs); 3-to-8 line decoder (3 inputs → 8 outputs, 74138 IC); truth table; logic diagram; enable input; expanding decoders — implementing 4-to-16 using two 3-to-8 decoders (with one address bit as enable); 5-to-32 decoder using four 3-to-8 decoders; BCD-to-decimal decoder (4 inputs → 10 outputs — invalid BCD states treated as don’t-cares); BCD-to-7-segment display decoder — seven-segment display structure (segments a, b, c, d, e, f, g); truth table for all 10 digits; K-map minimization for each segment; 74LS47 BCD-to-7-segment decoder IC
  • Encoder: converts one-of-many active inputs to a binary output code; opposite of decoder; 8-to-3 octal-to-binary encoder (8 inputs → 3 outputs); truth table; logic expression and diagram; decimal-to-BCD encoder (10 inputs → 4 BCD outputs); priority encoder — handles multiple simultaneous active inputs by encoding the highest-priority (highest-number) active input; priority encoder truth table uses “X” (don’t care) for lower-priority inputs; 74LS148 8-to-3 priority encoder IC
  • Multiplexer (MUX): data selector; selects one of 2ⁿ data inputs and routes it to single output based on n select lines; 4-to-1 MUX (4 data inputs, 2 select lines, 1 output); 8-to-1 MUX (8 inputs, 3 select lines, 1 output); 16-to-1 MUX (16 inputs, 4 select lines, 1 output); truth table and Boolean expression for 4-to-1 MUX: Y = S₁’S₀’I₀ + S₁’S₀I₁ + S₁S₀’I₂ + S₁S₀I₃; logic diagram; expanding MUXes — implementing 16:1 from two 8:1; 74LS151 8-to-1 MUX IC; implementing logic functions using MUX (connect variables to select lines, appropriate 0/1/variable/complement to data inputs — implements any function of n+1 variables with n-select MUX)
  • Demultiplexer (DMUX): data distributor; routes single input to one of 2ⁿ outputs based on n select lines; 1-to-4 DMUX (1 input, 2 select lines, 4 outputs); 1-to-16 DMUX; relationship between DMUX and decoder (decoder with enable pin acts as DMUX)

3.7.2 Parallel Adder and Parity Generator/Checker

  • 4-bit Binary Parallel Adder: four full adders cascaded with carry rippling from LSB to MSB (carry out of FA₀ → carry in of FA₁, etc.); 74LS83 4-bit binary full adder IC; parallel addition vs. serial addition; carry ripple delay — propagation delay increases with bit width; carry look-ahead adder (concept — generate and propagate signals for faster carry computation)
  • 4-bit Magnitude Comparator: comparing two 4-bit binary numbers A and B; three outputs — A>B, A=B, A<B; equality detection (A=B when A₃⊕B₃=0 AND A₂⊕B₂=0 AND A₁⊕B₁=0 AND A₀⊕B₀=0 — using XNOR); 74LS85 4-bit magnitude comparator IC; expanding to 8-bit comparison by cascading
  • 9-bit Parity Generator and Checker: even/odd parity review; parity generator — generates parity bit to be appended to data; parity checker — verifies received data + parity bit has correct parity; implementing with XOR chain (parity = XOR of all data bits for even parity); 9-bit system (8 data bits + 1 parity bit); 74LS280 9-bit parity generator/checker IC

3.8 Basic Concepts of Programmable Logic

  • Introduction to Programmable Logic Devices (PLDs): pre-manufactured ICs containing uncommitted (unprogrammed) logic arrays; programmed by user to implement desired functions; advantages over fixed-function ICs — reduced parts count, smaller board area, faster prototyping, design changes without hardware change; programming technologies — fuse-based (one-time programmable — OTP), UV-erasable (EPROM-based), electrically erasable (EEPROM-based), SRAM-based (volatile — needs power or configuration loading)
  • PROM (Programmable Read Only Memory) as PLD: AND array (fixed — decoder — all minterms), OR array (programmable — OR planes select which minterms to OR); user programs the OR connections; suitable for implementing functions up to moderate complexity; PROM program table — specifying which minterms to include in each output function
  • EPROM (Erasable Programmable ROM): PROM that can be erased by exposure to UV light (through quartz window in ceramic package) and reprogrammed; UV erasure takes 15–20 minutes (UV lamp); EEPROM (Electrically Erasable PROM) — erased electrically byte by byte; Flash memory as modern descendant of EEPROM (block erasure — faster)
  • PAL (Programmable Array Logic): AND array (programmable), OR array (fixed); simpler and less flexible than PROM but faster; user programs AND connections to create desired product terms; OR array connects fixed sets of product terms to outputs; designing with PAL — writing Boolean expression in SOP form, mapping to PAL programming table; PAL16L8 example (16 inputs, 8 outputs, AND-OR structure)
  • PLA (Programmable Logic Array): both AND array and OR array are programmable (most flexible — can share product terms between outputs); AND array generates product terms; OR array selects which product terms OR together for each output; PLA program table — listing product terms and which outputs they contribute to; example of designing PLA for two Boolean functions simultaneously; comparison — PROM (fixed AND, programmable OR), PAL (programmable AND, fixed OR), PLA (programmable AND, programmable OR); modern descendants — CPLDs, FPGAs (highly complex programmable logic — used in Nepal’s telecom equipment, test and measurement)

Unit 4: Counter and Registers (16 teaching hours — joint largest unit)

4.1 Flip-Flops — RS, JK, JK Master-Slave, D, T

  • Introduction to Latches and Flip-Flops: distinction — latch (level-sensitive — transparent when enable HIGH), flip-flop (edge-triggered — changes state only at clock edge); both are bistable multivibrators (two stable states — store 1 bit); fundamental memory elements of sequential circuits
  • SR (Set-Reset) Latch: constructed from cross-coupled NOR gates (active-HIGH inputs) or NAND gates (active-LOW inputs); NOR-based SR latch truth table: S=0,R=0 (no change/memory), S=1,R=0 (set Q=1), S=0,R=1 (reset Q=0), S=1,R=1 (forbidden — both outputs try to be 0, race condition on release); NAND-based SR latch (active-LOW) — operates with inverted inputs; graphical symbol; applications — debouncing mechanical switches
  • Clocked SR Flip-Flop: SR latch with clock enable (AND gates on inputs); latch is transparent only when CLK=1; level-triggered; same forbidden state issue as SR latch; truth table showing S, R, CLK, Q, Q’ values
  • JK Flip-Flop: improves on SR — J input like S (Set), K input like R (Reset), but J=K=1 causes toggle (Q = Q_prev’) — no forbidden state; characteristic table (J=0,K=0 → No change; J=0,K=1 → Reset; J=1,K=0 → Set; J=1,K=1 → Toggle); characteristic equation Q_next = JQ’ + K’Q; graphical symbol; excitation table (finding J,K inputs needed for desired Q → Q_next transition — used in counter design); issue with basic JK — race condition (if CLK remains HIGH too long, output can toggle multiple times — requires short clock pulse width)
  • JK Master-Slave Flip-Flop: solution to race condition; two latches cascaded — master latch (active when CLK=1, captures input) and slave latch (active when CLK=0, transfers to output); state changes once per complete clock cycle; pulse-triggered (1s catching problem — if input changes while CLK=1, master captures spurious value); graphical symbol; timing diagram showing master-slave operation
  • D (Data) Flip-Flop: single D input; on active clock edge, Q follows D (captures/stores D); prevents forbidden states by construction (K is always J’ — cannot have J=K=1 or J=K=0 simultaneously in equivalent JK terms); characteristic equation Q_next = D; characteristic table; excitation table (D=Q_next — simpler); positive edge-triggered (rising edge — small triangle on CLK input in symbol) vs. negative edge-triggered (bubble + triangle); used for registers, shift registers, pipeline stages; most common flip-flop in modern digital design
  • T (Toggle) Flip-Flop: single T input; when T=0 — no change; when T=1 — toggles output (Q_next = Q’); characteristic equation Q_next = T⊕Q; derived from JK by connecting J=K=T; used in binary counters (each stage toggles at half the previous frequency — divides by 2); excitation table
  • Level Triggering vs. Edge Triggering: level-triggered (transparent when clock at certain level — latch behavior — can change multiple times per clock cycle — timing-sensitive, race conditions); edge-triggered (changes only at rising or falling edge — more predictable — standard in modern synchronous design); setup time (minimum time data must be stable before active clock edge) and hold time (minimum time data must be stable after clock edge) — critical timing parameters; metastability (what happens when setup/hold violated)
  • Excitation Tables: for each flip-flop type, showing what input(s) are needed to achieve a desired state transition (Q_now → Q_next); essential tool for sequential circuit design (counter design, state machine design); summary:
    • SR: 0→0 (S=0,R=X), 0→1 (S=1,R=0), 1→0 (S=0,R=1), 1→1 (S=X,R=0)
    • JK: 0→0 (J=0,K=X), 0→1 (J=1,K=X), 1→0 (J=X,K=1), 1→1 (J=X,K=0)
    • D: 0→0 (D=0), 0→1 (D=1), 1→0 (D=0), 1→1 (D=1)
    • T: 0→0 (T=0), 0→1 (T=1), 1→0 (T=1), 1→1 (T=0)

4.2 Asynchronous and Synchronous Counters

  • Counter classification: modulus (MOD) number = number of distinct states in the count sequence; binary counter (MOD = 2ⁿ for n flip-flops); asynchronous (ripple) counters vs. synchronous counters
  • Asynchronous (Ripple) Counters: flip-flops not all clocked simultaneously; output of each flip-flop is the clock input of the next; changes ripple through the chain with cumulative propagation delay; easier to build but slower and can have spurious states during transitions (glitches); 3-bit ripple counter using T flip-flops (Q₀ toggles each clock, Q₁ toggles when Q₀ falls, Q₂ toggles when Q₁ falls)
  • Ripple Counter — Circuit, State Diagram, and Timing Waveforms: 3-bit binary ripple counter (MOD-8) — draw circuit with 3 T flip-flops; complete truth table of states (000 → 001 → 010 → … → 111 → 000); state diagram (circles = states, arrows = transitions); timing waveform (showing all flip-flop outputs vs. clock); frequency division — Q₀ at f/2, Q₁ at f/4, Q₂ at f/8 of clock frequency
  • Ring Counter — Circuit, State Diagram, and Timing Waveforms: shift register with output of last flip-flop fed back to input of first; single 1 (or 0) circulates through the register; MOD = n for n flip-flops (one state per flip-flop); 4-bit ring counter: states 1000 → 0100 → 0010 → 0001 → 1000; circuit diagram, state diagram, timing diagram; advantage — decoding outputs directly without decoder; disadvantage — inefficient (uses n flip-flops for MOD-n, whereas binary counter uses only log₂n flip-flops)
  • Modulus-10 Counter (Decade Counter/BCD Counter): counts 0–9 (MOD-10) then resets to 0; using feedback to force reset at count 10 (binary 1010); circuit and state diagram; timing waveforms; widely used in digital clocks and frequency measurement; note — when count reaches 10 (1010), the momentary state triggers asynchronous reset; 74LS90 decade counter IC
  • Modulus Counters (5, 7, 11) and Design Principles: general method for building MOD-N counter where N is not a power of 2: (a) Asynchronous design — start with enough flip-flops (≥ log₂N), use NAND gate to detect target count and feed to clear; example — MOD-5: clear when 0101 is reached (5 clock pulses from 0), using 3 flip-flops and NAND on Q₂Q₀; MOD-7: clear when 0111; MOD-11: clear when 1011; circuit diagram, state diagram for each
  • Synchronous Design of Counters: all flip-flops share the same clock — all change state simultaneously at each clock edge; no cumulative propagation delay; faster and no glitches; design procedure: (1) determine number of flip-flops (⌈log₂N⌉), (2) create state table (current state → next state), (3) use flip-flop excitation tables to find required inputs for each flip-flop at each state, (4) simplify input expressions using K-map, (5) draw circuit; synchronous MOD-10 counter; synchronous up-down binary counter (count direction controlled by a mode input)

4.3 Applications of Counters

  • Digital Watch: architecture of a digital watch using cascaded counters; starting from high-frequency crystal oscillator (e.g., 32,768 Hz crystal — 2^15 Hz — used in Nepal’s digital watches, clocks, RTCs); dividing down — 32,768 Hz → 1 Hz using 15 cascaded divide-by-2 stages; 1 Hz clock → 60-state seconds counter (MOD-60) → minutes counter (MOD-60) → hours counter (MOD-12 or MOD-24); 7-segment display decoders to display each digit; complete system block diagram; multiplexed display for multi-digit readout; RTC (Real Time Clock) chips (DS1307, DS3231) as integrated digital watch circuits
  • Frequency Counter: measures the frequency of an unknown input signal; block diagram — input signal → pulse shaper (Schmitt trigger — converts any waveform to clean pulses) → controlled gate (AND gate or tri-state buffer) → counter (counts pulses during fixed gate time — e.g., 1 second from precision timebase) → latch (holds count while counter resets) → BCD-to-7-segment decoder/display; gate time = 1 second → count directly displays Hz; gate time = 0.1 second → multiply count by 10 for Hz; precision of timebase determines accuracy

4.4 Registers

  • Register: group of flip-flops storing a multi-bit binary word; n flip-flops store n bits; parallel vs. serial loading and unloading
  • Serial In, Serial Out (SISO) Shift Register: data enters and leaves one bit at a time; 4-bit SISO using 4 D flip-flops in series; each clock pulse shifts data one position right; takes n clock pulses to fully load n-bit data and n more to fully unload; timing diagram; use — serial data communication (UART — Universal Asynchronous Receiver-Transmitter — used in Nepal’s serial data links, RS-232)
  • Serial In, Parallel Out (SIPO) Shift Register: data enters serially (one bit per clock); all bits available simultaneously at parallel outputs after n clocks; used for serial-to-parallel conversion (serial communication → parallel computer bus); 74LS164 SIPO shift register IC
  • Parallel In, Serial Out (PISO) Shift Register: all bits loaded simultaneously (parallel load); shifted out one bit at a time; parallel-to-serial conversion; load/shift control signal; 74LS165 PISO shift register IC; used in serial communication transmission
  • Parallel In, Parallel Out (PIPO) Shift Register: data loaded and read simultaneously; essentially a parallel register; acts as buffer or synchronizer; all bits clocked in and out at same time
  • Right Shift and Left Shift Register: bidirectional shift register can shift data left or right based on control signal; right shift (data moves towards LSB — divide by 2 for unsigned); left shift (data moves towards MSB — multiply by 2); 74LS194 4-bit universal shift register (supports SIPO, PISO, left shift, right shift) IC; applications — arithmetic operations (shift for multiply/divide by powers of 2), serial data communication, pattern generation

Unit 5: Sequential Logic Design (6 teaching hours)

  • Basic Models of Sequential Machines (Finite State Machines — FSM): sequential circuit output depends on both current input AND current state (stored in flip-flops); formalized as Finite State Machine; two models:
    • Moore Model: outputs depend only on the current state (not directly on inputs); output associated with states; output changes synchronously with state changes; easier to design and analyze; common in digital control systems
    • Mealy Model: outputs depend on both current state and current inputs; output associated with transitions; output may change asynchronously with input changes (may cause glitches); generally requires fewer states than equivalent Moore machine for same function
    • Comparison table: Moore vs. Mealy — output function, number of states, output timing, glitch susceptibility, use cases
  • Concept of State: state = memory of relevant past history of the circuit (captured in flip-flop values); each unique combination of flip-flop values = one state; n flip-flops → up to 2ⁿ states
  • State Diagram: graphical representation of FSM; circles/ovals represent states (labeled with state name and Moore output if Moore model); arrows represent state transitions (labeled with input/Mealy-output for Mealy model; or just input for Moore model); self-loops (transition back to same state); constructing state diagram from verbal description of desired behavior
  • State Table: tabular form of state diagram; columns — Current State, Input, Next State, Output; one row per state-input combination; essential step in sequential circuit design; converting state diagram ↔ state table
  • State Reduction (Minimization) through Partitioning: reducing the number of states (fewer flip-flops needed — cheaper, simpler circuit) while maintaining equivalent behavior; Partitioning method — group states with same output; for each partition group, check if states in the group transition to the same partition groups for all inputs — if yes, group remains; if not, split; continue until no more splits; states in same final partition are equivalent and can be merged; results in minimum-state FSM
  • Implementation of Synchronous Sequential Circuits — Design Procedure:
    • Step 1: Problem specification — describe desired behavior in words or state diagram
    • Step 2: State diagram and state table — draw complete state diagram; convert to state table
    • Step 3: State reduction — apply partitioning to minimize states (if needed)
    • Step 4: State assignment — assign binary codes to each state (choosing good assignment can simplify combinational logic)
    • Step 5: Choose flip-flop type (D, JK, T) for implementation
    • Step 6: Derive next-state equations — using state table and chosen flip-flop excitation tables; create excitation table (shows required flip-flop inputs for each state transition); simplify using K-map
    • Step 7: Derive output equations — K-map simplification
    • Step 8: Draw logic circuit — flip-flops + combinational logic for next-state and output functions
  • Use of Flip-Flops in Realizing Sequential Machines: applying the above design procedure to realize Moore and Mealy state machines using D flip-flops (simplest — D input = next state function) or JK flip-flops (uses JK excitation table for each state bit’s transition)
  • Counter Design using FSM Approach: demonstrating that counter design is a special case of sequential machine design where output = state; designing MOD-N counters by specifying state sequence → deriving flip-flop input equations; synchronous counter design using JK flip-flops (classic exam problem): (1) state table (current count → next count for all states), (2) JK excitation table lookup for each flip-flop bit, (3) K-map simplification of J and K input functions, (4) circuit diagram

Laboratory Activities (25 Experiments)

Laboratory work for CACS105 runs 2 hours per week, totalling approximately 30 lab hours. Students work on project boards (breadboards) using 74-series TTL ICs (7400 series — common in TU BCA labs across Nepal), connecting ICs, verifying truth tables, and observing timing behavior. The lab report format requires: Title, Objectives, Apparatus, Theory (Introduction, Functional Expression, Circuit Diagram, Truth Table), Procedure, Result, and Remarks.

  • Experiment 1: IC familiarization — nomenclature (part number, manufacturer prefix, temperature grade, package suffix), datasheet reading (pin diagram, truth table, Vcc and GND pins, propagation delay, power supply requirements), IC base/socket, project board (breadboard) layout (power rails, tie points), power supply connections (+5V Vcc, GND), input switches, output LEDs
  • Experiment 2: Basic Gates — AND (7408), OR (7432), NOT/Inverter (7404) — connect ICs, apply all input combinations, verify truth table, draw timing diagram
  • Experiment 3: Universal Gates — NAND (7400) and NOR (7402) — verify truth tables; demonstrate NAND universality (implement NOT, AND, OR using only NAND gates); demonstrate NOR universality (implement NOT, AND, OR using only NOR gates)
  • Experiment 4: Ex-OR (7486) and Ex-NOR gates — verify truth tables; demonstrate XOR as inequality detector; demonstrate XNOR as equality detector
  • Experiment 5: Realize Basic gates using NAND gate — implement NOT, AND, OR, AND-OR networks using only 7400 NAND IC; verify with truth tables
  • Experiment 6: Realize Basic gates using NOR gate — implement NOT, AND, OR networks using only 7402 NOR IC; verify with truth tables
  • Experiment 7: Prove DeMorgan’s Theorems using gates — implement (A+B)’ and A’B’ separately, show outputs are identical; implement (AB)’ and A’+B’ separately, show outputs are identical; verify with complete truth tables
  • Experiment 8: Implement given Boolean function in both SOP and POS forms using logic gates; simplify function using K-map first; implement minimized SOP; implement minimized POS; verify both give same outputs; demonstrate circuit equivalence
  • Experiment 9: Half Adder and Full Adder — implement Half Adder (XOR + AND); implement Full Adder using two Half Adders + OR gate; verify truth tables; connect four Full Adders as 4-bit ripple carry adder and verify with binary additions
  • Experiment 10: Half Subtractor and Full Subtractor — implement Half Subtractor (XOR + AND with NOT); implement Full Subtractor; verify truth tables
  • Experiment 11: 4-bit Binary Parallel Adder — verify operation of 74LS83 (or equivalent) 4-bit binary full adder IC; add various 4-bit numbers; observe carry out and sum outputs; test with carry input
  • Experiment 12: Octal-to-Binary Encoder — implement 8-to-3 encoder; verify that pressing each of 8 input switches produces correct 3-bit binary output; note that only one input should be HIGH at a time
  • Experiment 13: Decimal-to-BCD Encoder — implement or verify 10-to-4 BCD encoder; pressing key 0–9 produces corresponding 4-bit BCD output
  • Experiment 14: 3-to-8 Line Decoder (74138) — verify operation; apply all 8 input combinations (A2 A1 A0); verify exactly one output is LOW (active-low outputs in 74138) for each input; demonstrate enable inputs; demonstrate use as DMUX
  • Experiment 15: BCD-to-Decimal Decoder — connect 74LS42 (or similar) BCD-to-decimal decoder; apply BCD codes 0000–1001; verify corresponding output activates; observe that invalid BCD codes (1010–1111) produce no output
  • Experiment 16: BCD-to-7-Segment Display Decoder — connect 74LS47 (common anode) or 74LS48 (common cathode) to 7-segment LED display; apply BCD codes 0–9; verify correct digit displayed; demonstrate ripple blanking input (RBI) for leading zero suppression; connect multiple digits for multi-digit display
  • Experiment 17: 16:1 Multiplexer — implement using two 74LS151 (8:1 MUX) ICs; connect data inputs; apply various select input combinations; verify correct data input appears at output
  • Experiment 18: 1:16 Demultiplexer — implement using two 74LS154 (1:16 DMUX) or 74138 ICs; apply single data input; apply select combinations; verify data routed to correct output
  • Experiment 19: Flip-Flop verification — construct and verify (i) SR latch (NAND gates), (ii) JK flip-flop (74LS73 or similar), (iii) JK Master-Slave flip-flop (74LS76), (iv) D flip-flop (74LS74), (v) T flip-flop (JK with J=K=1 or 74LS74 with Q’ fed back to D); verify characteristic table and excitation table for each
  • Experiment 20: 3-bit Synchronous Binary Counter — implement or verify 74LS163 (or similar) as synchronous binary counter; observe CLK, Q₀, Q₁, Q₂ waveforms on oscilloscope (or LEDs showing sequential count); verify count sequence 000→001→…→111→000; measure frequency division
  • Experiment 21: 3-bit Asynchronous Binary Counter — implement 3-bit ripple counter using 74LS93 or T flip-flops cascaded; observe that each stage frequency is half previous stage; observe propagation delay (ripple) between stages on oscilloscope; count sequence 000→001→…→111→000
  • Experiment 22: MOD-10 Counter Design — implement decade counter using feedback reset (NAND gate detecting count 10 and clearing asynchronously) or use 74LS90 decade counter IC; verify 0–9 count sequence; connect 7-segment display to show decimal digit
  • Experiment 23: Shift Register verification — verify operation of all four modes using 74LS194 (universal shift register) or separate ICs: (i) SISO — clock in serial data, observe shifting; (ii) SIPO — clock in serial data, observe all parallel outputs after n clocks; (iii) PISO — parallel load all bits, clock out serially; (iv) PIPO — parallel load, observe immediate parallel output; timing diagrams for each mode
  • Experiment 24: Digital Watch Design — implement complete digital watch (or portion): crystal oscillator → 1 Hz divider chain → MOD-60 seconds counter → MOD-60 minutes counter → MOD-12 hours counter → BCD-to-7-segment decoders → 7-segment displays; verify timekeeping; demonstration of complete integrated system
  • Experiment 25: Frequency Counter Design — implement frequency counter: unknown input → Schmitt trigger (for signal conditioning) → AND gate controlled by 1-second gate signal (from precise timebase) → 4-decade BCD counter (4× 74LS90) → 4× BCD-to-7-segment decoder/display; verify that display shows input frequency in Hz; test with known frequency inputs

Evaluation Scheme

  • Theory Examination (End-of-Semester): 60 marks | Pass marks: 24 | Time: 3 hours
    • Group A: 10 objective (MCQ) questions × 1 mark = 10 marks (all compulsory)
    • Group B: attempt any 6 from 7 short questions × 5 marks = 30 marks
    • Group C: attempt any 2 from 3 long questions × 10 marks = 20 marks
  • Internal Assessment: 20 marks — Mid-term exam (5) + Pre-final exam (5) + Assignment (5) + Attendance (5)
  • Practical Assessment: 20 marks — Practical viva (10) + Lab reports (5) + Attendance (5) — assessed by external examiner assigned by Dean Office, FOHSS
  • Total: 100 marks | All three components must be passed separately

Recommended Textbooks and References

Primary Textbooks (as listed in the official CACS105 syllabus)

  • Thomas L. Floyd. Digital Fundamentals, 11th Edition. Pearson/PHI — the most recommended and widely used textbook for this course; comprehensive coverage of all CACS105 topics with excellent circuit diagrams, IC datasheets, and worked examples; directly mapped to the official syllabus
  • Morris Mano. Digital Design, 5th Edition. PHI (Pearson) — rigorous, mathematically thorough treatment of digital logic and sequential machine design; essential for Unit 5 (Sequential Logic Design); classic text used globally
  • Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss. Digital Systems: Principles and Applications, 10th Edition. PHI — good practical treatment with emphasis on real IC applications; useful companion for lab work

Reference Books (as listed in the official CACS105 syllabus)

  • B.R. Gupta and V. Singhal. Digital Electronics. S.K. Kataria and Sons, India
  • W.I. Fletcher. An Engineering Approach to Digital Design. PHI
  • Millman and Halkias. Integrated Electronics. McGraw-Hill
  • V.K. Puri. Digital Electronics. Tata McGraw-Hill
  • Anil K. Maini. Digital Electronics: Principles, Devices and Applications. Wiley (particularly good for Programmable Logic Devices — PLD unit)
  • Roger Tokheim. Digital Electronics: Principles and Applications, 8th Edition. McGraw-Hill (practical, accessible, excellent for counters and registers)

Difference Between NEB Grade 12 Computer Science and TU BCA Digital Logic

NEB Grade 12 Computer Science covers Number Systems (binary, octal, hexadecimal conversions and Boolean logic basics — AND, OR, NOT, NAND, NOR, XOR truth tables) in Unit 2, providing useful background for CACS105 Units 1–2. However, TU BCA Digital Logic goes dramatically further across every dimension. Boolean algebra is treated formally (postulates, theorems with proofs, De Morgan’s theorems with full derivation, duality principle, canonical SOP/POS forms). The K-map simplification method — entirely absent from NEB — occupies a major portion of Unit 3 and is the primary circuit minimization tool for the entire course. All combinational building blocks (adders, subtractors, encoders, decoders, MUXes, DMUXes, PLDs) are designed from scratch using systematic procedures. Sequential circuits — flip-flops, counters, registers, and state machines — are entirely new content with no NEB equivalent. The formal sequential machine design methodology (state diagram → state table → state reduction → excitation table → K-map → circuit) is university-level digital design with no parallel in the NEB curriculum.

Tips to Score High in CACS105

  • Master number system conversions until they are instant: Unit 2 conversions appear in Group A (MCQs) and Group B (short questions) in every past paper. Practice converting between binary, octal, hexadecimal, and decimal — both integer and fractional parts — until you can do them accurately in under 2 minutes. BCD addition and Gray code conversion are also regularly tested.
  • For Boolean algebra, learn proofs not just results: Group B questions on Boolean algebra frequently ask “Prove De Morgan’s Theorem” or “Prove the absorption law using Boolean postulates.” Memorizing the theorem result is insufficient — know the step-by-step proof using truth tables (perfect induction) or algebraic manipulation using postulates.
  • K-map is the highest-value skill to master: K-map simplification appears in almost every past paper — often as a Group B (5 marks) or Group C (10 marks) question. Practice: (a) constructing K-map from a Boolean expression or truth table, (b) identifying all prime implicants, (c) selecting essential prime implicants, (d) writing minimized SOP and POS expressions, (e) drawing the minimized circuit. Practice with don’t-cares. Speed and accuracy here are directly marks.
  • Draw every circuit with correct symbols and labels: Group C questions on adders, decoders, multiplexers, and sequential circuits are graded primarily on the correctness and completeness of the circuit diagram. Use standard IEEE/ANSI symbols for all gates and flip-flops; label all inputs, outputs, and intermediate signals; show truth tables alongside circuits. Neat, clearly labeled diagrams score full marks even if your derivation has a minor error.
  • Sequential design (flip-flop + counter) questions are Group C favourites: Both past exam sets include counter design questions — “Design a MOD-5 counter using JK flip-flop” (5 marks, Group B) and “Design a 4-bit binary ripple counter with circuit, state, and timing diagram” (10 marks, Group C) appear consistently. Master the design procedure: state table → JK excitation table → K-map → J and K input equations → circuit. Practice this for MOD-5, MOD-7, MOD-10, and 2-bit up/down counters.
  • Complete all 25 lab experiments and maintain clean lab reports: The 20-mark practical assessment (viva 10 + reports 5 + attendance 5) is awarded by an external examiner. Examiners in viva sessions consistently ask about IC numbers (7400, 7408, 7486, 74138, 74LS194), pin diagrams, what you observed in each experiment, and why circuits behave as they do. Know the IC numbers for all components you used.
  • Solve both past exam paper sets (Set A and Set B) from 2018: These are the official TU FOHSS past papers for CACS105 and directly reveal the MCQ style (Gray code, NAND gate theory, K-map results, flip-flop behavior, counter cascading), Group B question types (complement methods, universal gates, K-map, encoders, flip-flop circuits, counter design, shift registers), and Group C depth expected (decoder expansion, digital watch, asynchronous counter with timing, JK counter design). Practising these under timed conditions (3 hours) is the most effective exam preparation.

Frequently Asked Questions (FAQs)

What is the course code and credit hours for Digital Logic in TU BCA?

The course code is CACS105, worth 3 credit hours. It runs at 5 hours per week (3 theory + 2 practical). Full marks: 60 (theory) + 20 (practical) + 20 (internal) = 100. Pass mark for theory: 24 out of 60.

How many units are in CACS105 and what are the teaching hours?

CACS105 has 5 units: Unit 1 (Introduction — 2 hours), Unit 2 (Number System — 5 hours), Unit 3 (Combinational Logic Design — 16 hours, largest), Unit 4 (Counter and Registers — 16 hours, joint largest), and Unit 5 (Sequential Logic Design — 6 hours). The total is 45 theory hours.

Why are NAND and NOR called universal gates?

NAND and NOR are called universal gates because any Boolean function — and therefore any digital circuit — can be implemented using only NAND gates alone, or only NOR gates alone, without needing any other gate type. This is because NOT, AND, and OR can each be implemented using NAND gates (or NOR gates) alone, and since {NOT, AND, OR} is a functionally complete set, NAND alone (and NOR alone) is also functionally complete. In practical IC manufacturing, NAND gates are also simpler and faster to implement in CMOS technology than AND gates — making this universality both theoretically significant and practically useful.

What is the difference between a latch and a flip-flop?

A latch is level-sensitive (or transparent) — it responds to its inputs continuously while the enable/clock signal is at a certain level (HIGH or LOW), and can change state multiple times per clock period. A flip-flop is edge-triggered — it responds to inputs only at the active edge (rising or falling) of the clock signal, changing state exactly once per clock cycle. This edge-triggering makes flip-flops more predictable and reliable in synchronous digital systems, which is why virtually all modern sequential circuits use flip-flops rather than latches.

What is the difference between synchronous and asynchronous counters?

In an asynchronous (ripple) counter, all flip-flops do not share the same clock. The clock input of each flip-flop after the first is driven by the output of the previous flip-flop, so state changes ripple through the chain with cumulative propagation delay. This makes ripple counters simple but potentially slower and prone to glitches. In a synchronous counter, all flip-flops share the same clock signal and change state simultaneously at each clock edge, eliminating ripple delay and glitches. Synchronous counters are faster, more reliable, and preferred in high-speed digital systems.

How many lab experiments are there in CACS105?

The official CACS105 lab syllabus lists 25 laboratory activities, ranging from IC familiarization (Experiment 1) through basic gate verification (Experiments 2–7), Boolean function implementation (Experiment 8), adders and subtractors (9–11), encoders, decoders, MUXes, DMUXes (12–18), flip-flop verification (19), counter experiments (20–22), shift register experiments (23), and integrated system projects — digital watch (24) and frequency counter (25).

Where can I find CACS105 notes and past papers?

You can find study resources on nneducation.com. The official CACS105 syllabus PDF is also embedded at the top of this page. Both official past exam paper sets (Set A and Set B — 2018 TU FOHSS board exam) are included in the micro-syllabus document. Notes and solved exercises are available on notebahadur.com, hamrocsit.com, and Studocu.com.

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